Field of the Disclosure
The present disclosure relates generally to data processing devices and methods and more particularly to data processing using a type of execute-only memory space.
Description of the Related Art
A particular trend with embedded microcontrollers is the increasing need to prevent information stored in memory, such as program code, from being copied by unauthorized sources. One type of memory protection uses the concept of execute-only memory to protect code images from unauthorized accesses by allowing instruction access requests to memory space that is designated as execute-only memory (XOM), while preventing operand access requests, also referred to as data access requests to XOM.
XOM is readily implemented with data processor architectures that support instructions of sufficient length, such as data processors having an Instruction Set Architecture (ISA) that supports variable-length instructions. The use of XOM with other data processor architectures, such as data processors having an ISA with small fixed-length instructions, can be more difficult to implement. The additional complexity of implementing XOM with data processors that support fixed-length instructions is apparent by comparing the manner in which fixed and variable-length ISA's can add a constant value to a register location.
For example, a data processor that supports variable-length instructions can access an instruction from XOM that includes an opcode, and an operand of variable size, e.g., 8-bits, 16-bits, or 32-bits, where the operand is a constant value that is referred to as an immediate operand by virtue of being part of the instruction itself. Thus, a 32-bit data processor that supports variable-length instructions can execute an ADD instruction having a length that is sufficient to accommodate an opcode identifying the instruction, register identifiers indicating source/destination locations of operands/resultants, and a 32-bit immediate operand that is a constant to be added to the source/destination. For purposes of discussion, it is presumed that such an ADD instruction is a 48-bit instruction that includes a 32-bit immediate value, e.g., a constant, that is to be added to a designated register location of the 16-bit operation code (opcode) that defines the ADD operation including register identifiers.
In comparison, a data processor having fixed-length 32-bit instructions, or smaller, cannot access an instruction from XOM that includes both an opcode and a 32-bit immediate operand. Instead, a fixed-length instruction, e.g. an ADD instruction performing the same function as the ADD instruction described above, needs to fetch the 32-bit operand using a separate data fetch from that used to retrieve the instruction itself.
For example, instead of including an immediate operand, a 32-bit add instruction can include an index field having a value that is added to the program counter to indicate where a 32-bit addend, e.g., a constant, is stored in memory. Determining the address of an operand in this manner is referred to as program counter-relative (PC-relative) addressing. Thus, a fixed length 32-bit instruction can include an opcode of an ADD instruction that uses PC-relative addressing, a register indicator identifying a source/destination location of an operand/resultant, and an index, presumed to be eight-bits, that is added to the program counter of the instruction to identify a target address at which a 32-bit constant value is stored that will be added to the destination location identified by the register indicator. Thus, while a fixed-length instruction ISA can include an ADD instruction that results in a 32-bit constant being added to a destination register, the 32-bit constant is not accessed by the same instruction fetch mechanism that retrieved the ADD instruction, but instead is accessed by a separate operand fetch from a location of memory that is within a maximum offset range of the program counter of the instruction.
It will be appreciated that in order to use XOM to protect fixed-length instructions that use PC-relative addressing, it is necessary to partition the memory space to have at least one non-execute-only memory (nXOM) location within 256 words of the XOM location where the PC-relative instruction is stored, wherein the range of the index to be added to the PC of instruction is 256. Supporting small amounts of nXOM for read only data storage near instruction code stored in XOM space results in the need to partition XOM and nXOM using a relatively fine granularity, as opposed to the XOM/nXOM granularity needed when using variable-length instructions that store and access the constant values as immediate operands that are part of the instructions themselves. Implementing systems that need finely partitioned XOM/nXOM space are more costly than systems that use coarsely partitioned XOM/nXOM space. Alternatively, fixed-length instruction systems can avoid the use of PC-relative commands; however, this can result in operand requests to distant memory locations that require additional resources and time to access the distant locations.